Leakage current-based testing of CMOS ICs - Potentials, IEEE

of the Complementary Metal Oxide Semiconductor (CMOS), realized that a CMOS circuit does not consume current under a steady state operation. This is because there is no direct path from the supply rail (VDD) to the ground rail (VSS). The two complementary transistors operate in such a way that they are never simultaneously ON, except for a brief period during switching. Thus, static power consumption of a CMOS circuit is very small compared to its bipolar equivalent. The current that flows from VDD to VSS when the inputs are stable is called leakage current and is denoted as IDDQ. The test method relying on this measurement is called the IDDQ test. The basic theme of IDDQ testing can be better understood with the help of an inverter circuit shown in Fig. 1a). In the absence of a defect and when the input is stable, the quiescent current flowing from VDD to ground is low (since there is no direct path from VDD to ground), as shown in Fig. 1b). In the presence of a defect (e.g. source-drain short, as shown in Fig. 1a)), however, significant current flows through the transistors. By measuring the elevated leakage current, it is possible to identify a defective chip. Note that for the defect shown in Fig. 1(a), IDDQ is high only when the defect is excited i.e. when the input is logic high. Such a defect is called an active or pattern-dependent defect. A defect that results in high leakage current independent of the input pattern is called a passive or pattern-independent defect (e.g. VDD-to-ground short). Notice also that several other bridging defects in the circuit (e.g. gate-to-source short, inter-gate bridges, etc.) that result in